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Browsing by Author Rao, V. Ramgopal

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Issue DateTitleAuthor(s)
2001-10A study of hot-carrier induced interface-trap profiles in lateral asymmetric channel MOSFETs using a novel charge pumping techniqueRao, V. Ramgopal
2020-01A study of surface stress and flexural rigidity of symmetrically and asymmetrically biofunctionalized microcantileversRao, V. Ramgopal
1998-09A Study of the Effect of Plasma Etch Damage on Sub-Micron MOSFET's Flicker Noise PropertiesRao, V. Ramgopal
2013-08Sub 0.5V Operation of Performance Driven Mobile Systems Based on Area Scaled Tunnel FET DevicesRao, V. Ramgopal
1998-10Sub-0.18 /spl mu/m SOI MOSFETs using lateral asymmetric channel profile and Ge pre-amorphization salicide technologyRao, V. Ramgopal
2001-07Sub-100 nm CMOS circuit performance with high-K gate dielectricsRao, V. Ramgopal
2008Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?Rao, V. Ramgopal
2020-09Sub-50-mV Nanoelectromechanical Switch Without Body BiasRao, V. Ramgopal
2004-07Sub-threshold Swing Degradation due to Localized Charge Storage in SONOS MemoriesRao, V. Ramgopal
2005-03Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applicationsRao, V. Ramgopal
2002Suppression of boron penetration by hot wire CVD polysiliconRao, V. Ramgopal
2001Suppression of Parasitic BJT Action in Single Pocket Thin Film Deep Sub-Micron SOI MOSFETsRao, V. Ramgopal
2020-02Surface Modification of AlN Using Organic Molecular Layer for Improved Deep UV Photodetector PerformanceRao, V. Ramgopal
2020-12Switched-Capacitor-Assisted Power Gating for Ultra-Low Standby Power in CMOS Digital ICsRao, V. Ramgopal
2013-10A TFT embedded cantilever (CantiFET) platform for sensor applicationsRao, V. Ramgopal
2016-01A Thermal Aware Device Design Considerations for Nano-scale SOI and Bulk FinFETsRao, V. Ramgopal
2016-04Thikness dependence investigation of the mutual inductance link in concentric planar transformersRao, V. Ramgopal
2003Thin film single halo (SH) SOI nMOSFETs - hot carrier reliability for mixed mode applicationsRao, V. Ramgopal
2011-06Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization GuidelinesRao, V. Ramgopal
2011-07A Tunnel FET for VDD Scaling Below 0.6 V With a CMOS-Comparable PerformanceRao, V. Ramgopal