DSpace logo

Browsing by Author Rao, V. Ramgopal

Jump to: 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
or enter first few letters:  
Showing results 24 to 43 of 371 < previous   next >
Issue DateTitleAuthor(s)
2009Benchmarking the device performance at sub 22 nm node technologies using an SoC frameworkRao, V. Ramgopal
2010A Binary Tunnel Field Effect Transistor with a Steep Sub-threshold Swing and Increased ON CurrentRao, V. Ramgopal
2009-10Bio-functionalization of silicon nitride-based piezo-resistive microcantileversRao, V. Ramgopal
2007-08Border-Trap Characterization in High-κ Strained-Si MOSFETsRao, V. Ramgopal
2015Bottom-up meets top down: An integrated approach for nano-scale devicesRao, V. Ramgopal
2011-08Bottom-up method for work function tuning in high-k/metal gate stacks in advanced CMOS technologiesRao, V. Ramgopal
2009-02A CAD-compatible closed form approximation for the inversion charge areal density in double-gate MOSFETsRao, V. Ramgopal
1999-09Capacitance Degradation due to Fringing Field in Deep Sub-Micron MOSFETs with High-K Gate DielectricsRao, V. Ramgopal
2015Carbon black nanocomposite piezoresistive microcantilevers with reduced percolation thresholdRao, V. Ramgopal
1999Channel engineering for high speed sub-1.0 V power supply deep sub-micron CMOSRao, V. Ramgopal
2009-06Characterization of interface and oxide traps in Ge pMOSFETs based on DCIV techniqueRao, V. Ramgopal
2001-10Characterization of lateral asymmetric channel (LAC) thin film SOI MOSFETsRao, V. Ramgopal
2021-11Charge Carrier Doping As Mechanism of Self-Assembled Monolayers Functionalized Electrodes in Organic Field Effect TransistorsRao, V. Ramgopal
1998-05Charge injection using gate-induced-drain-leakage current for characterization of plasma edge damage in CMOS devicesRao, V. Ramgopal
1997-03Charge trapping behaviour in deposited and grown thin metal-oxide-semiconductor gate dielectricsRao, V. Ramgopal
2009Chemical Vapor Deposition Precursors for High Dielectric Oxides: Zirconium and Hafnium OxideRao, V. Ramgopal
2003-10CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parametersRao, V. Ramgopal
2012Circuit Optimization at 22nm Technology NodeRao, V. Ramgopal
2007Circuit Performance Improvement Using PDSOI-DTMOS Devices with a Novel Optimal Sizing Scheme Considering Body ParasiticsRao, V. Ramgopal
2008-06Closed Form Current and Conductance Model for Symmetric Double-Gate MOSFETs using Field-dependent Mobility and Body DopingRao, V. Ramgopal