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BITS Pilani Institutional Repository
Browsing by Author Asati, Abhijit
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Showing results 12 to 31 of 58
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Issue Date
Title
Author(s)
2022-07
Dedicated hardware architecture for localizing iris in VW images
Asati, Abhijit
;
Gupta, Anu
2015
Design and ASIC implementation of column compression Wallace/Dadda multiplier in sub-threshold regime
Gupta, Anu
;
Asati, Abhijit
2012
Design of a Static Current Simulator Using Device Matrix Approach
Asati, Abhijit
2015
Design of ultra low power flip flops in sub-threshold region for bio-medical application in 45nm, 32nm and 22nm technologies
Asati, Abhijit
2016
Effectiveness of body bias & hybrid logic: An energy efficient approach to design adders in sub-threshold regime
Gupta, Anu
;
Asati, Abhijit
2013
Generic modified Baugh Wooley multiplier
Asati, Abhijit
2017-09
Hardware Accelerators for Iris Localization
Gupta, Anu
;
Asati, Abhijit
2017-04
Hardware implementation of a novel edge-map generation technique for pupil detection in NIR images
Gupta, Anu
;
Asati, Abhijit
2012
Hardware software co-design using profiling and clustering
Asati, Abhijit
2009-05
A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Logic Design Style With Improved Performance
Asati, Abhijit
;
Shekhar, Chandra
2020-10
High-Level synthesis assisted design and verification framework for automotive radar processors
Asati, Abhijit
;
Shekhar, Chandra
2020-05
High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications
Asati, Abhijit
;
Shekhar, Chandra
2008
A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic
Asati, Abhijit
;
Shekhar, Chandra
2009
A high-speed, hierarchical 16×16 array of array multiplier design
Asati, Abhijit
;
Shekhar, Chandra
2021-05
An Improved DVFS Circuit & Error Correction Technique
Asati, Abhijit
2008
An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style
Asati, Abhijit
;
Shekhar, Chandra
2021
An Improved Power Gating Technique with Data Retention and Clock Gating
Asati, Abhijit
2021-12
Integrated Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes
Asati, Abhijit
2014
Iris based biometric identification system
Asati, Abhijit
2015
Iris localization based on integro-differential operator for unconstrained infrared iris images
Gupta, Anu
;
Asati, Abhijit