Skip navigation
Home
Browse
Communities
& Collections
Browse Items by:
Issue Date
Author
Title
Subject
Help
Sign on to:
My DSpace
Receive email
updates
Edit Profile
BITS Pilani Institutional Repository
Browsing by Author Asati, Abhijit
Jump to:
0-9
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
or enter first few letters:
Sort by:
title
issue date
submit date
In order:
Ascending
Descending
Results/Page
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Authors/Record:
All
1
5
10
15
20
25
30
35
40
45
50
Showing results 33 to 52 of 58
< previous
next >
Issue Date
Title
Author(s)
2016
Leakage Immune 9T-SRAM Cell in Sub-threshold Region
Gupta, Anu
;
Asati, Abhijit
2015
Leakage Immune Modified Pass Transistor Based 8T SRAM Cell in Subthreshold Region
Gupta, Anu
;
Asati, Abhijit
2009
Logic Design Style based NBTI Degradation Study using Verilog
Asati, Abhijit
2021-12
Low-Area, High-Throughput Field-Programmable Gate Array Implementation of Microprocessor Without Interlocked Pipeline Stages
Asati, Abhijit
;
Shekhar, Chandra
2017-09
Low-latency median filter core for hardware implementation of 5 × 5 median filtering
Gupta, Anu
;
Asati, Abhijit
2019-09
Low-voltage, low-power SRAM circuits using subthreshold design technique
Asati, Abhijit
;
Gupta, Anu
2018-10
Memory-efficient architecture of circle Hough transform and its FPGA implementation for iris localisation
Gupta, Anu
;
Asati, Abhijit
2016-02
A modular approach to random task graph generation
Asati, Abhijit
2016
A Novel Edge-Map Creation Approach for Highly Accurate Pupil Localization in Unconstrained Infrared Iris Images
Gupta, Anu
;
Asati, Abhijit
2018
Novel low-power and stable SRAM cells for sub-threshold operation at 45 nm
Gupta, Anu
;
Asati, Abhijit
2021-11
A Novel Method for Suitable Hyperparameter Selection in an Accurate Convolutional Neural Network Architecture
Asati, Abhijit
;
Shenoy, Meetha V.
2009-08
A Novel Redundant Binary Number to Natural Binary Number Converter
Gupta, Anu
;
Shekhar, Chandra
;
Asati, Abhijit
2018
Optimizing the Ratio of Number of Tubes in PCNTFET to NCNTFET for Digital Circuits
Asati, Abhijit
2020-11
Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications
Asati, Abhijit
;
Shekhar, Chandra
2015
Power-aware Design of Logarithmic Prefix Adders in Sub-threshold Regime: A Comparative Analysis
Gupta, Anu
;
Asati, Abhijit
2012
A Purely MUX Based High Speed Barrel Shifter VLSI Implementation Using Three Different Logic Design Styles
Asati, Abhijit
;
Shekhar, Chandra
2021-02
Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm
Asati, Abhijit
;
Shekhar, Chandra
2020-07
RETRACTED ARTICLE: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications
Asati, Abhijit
;
Shekhar, Chandra
2022-07
Retraction Note to: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications
Asati, Abhijit
2016
ROM based logic design for base-2 exponential and logarithm converter using fixed point number representation
Asati, Abhijit