Browsing by Subject 45 nm CMOS technology
Showing results 1 to 11 of 11
| Issue Date | Title | Author(s) |
| 2019-02 | Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology | Vidhyadharan, Sanjay |
| 2023-01 | Fast and Low-Power CMOS and CNFET based Hysteresis Voltage Comparator | Vidhyadharan, Sanjay |
| 2020-01 | Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node | Vidhyadharan, Sanjay |
| 2020-10 | An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger | Vidhyadharan, Sanjay |
| 2021-04 | Mux Based Ultra-Low-Power Ternary Adders and Multiplier implemented with CNFET and 45 nm MOSFETs | Vidhyadharan, Sanjay |
| 2019 | Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications | Vidhyadharan, Sanjay |
| 2021-05 | A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM | Vidhyadharan, Sanjay |
| 2020-03 | A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder | Vidhyadharan, Sanjay |
| 2020-10 | TiO2−x–TiO2 Memristor Applications for Programmable Analog VLSI Circuits at 45 nm CMOS Technology Node | Vidhyadharan, Sanjay |
| 2021-01 | An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder | Vidhyadharan, Sanjay |
| 2020-11 | An ultra-low-power CNFET-based improved Schmitt triggerdesign for VLSI sensor applications | Vidhyadharan, Sanjay |
