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Browsing by Author Chaturvedi, Nitin

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Issue Date	Title	Author(s)
2022-07	Ab Initio Study of Carbon Nanotube Field Effect Transistor Gas Sensor for Detection of Ammonia and Nitrogen Dioxide Gas	Gupta, Navneet; Chaturvedi, Nitin
2010-12	Adaptive Block Pinning Based: Dynamic Cache Partitioning for Multi-core Architectures	Chaturvedi, Nitin
2013	An Adaptive Block Pinning Cache for Reducing Network Traffic in Multi-core Architectures	Chaturvedi, Nitin
2013	An adaptive coherence protocol with adaptive cache for multi-core architectures	Chaturvedi, Nitin
2015-07	An adaptive migration–replication scheme (AMR) for shared cache in chip multiprocessors	Chaturvedi, Nitin
2010	Adaptive Zone-Aware Multi-bank on Chip last level L2 Cache Partitioning for Chip Multiprocessors	Chaturvedi, Nitin
2019	A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications	Chaturvedi, Nitin
2017	A comparative analysis of read/write assist techniques on performance & margin in 6T SRAM cell design	Chaturvedi, Nitin
2017	Design and analysis of 6T SRAM cell with NBL write assist technique using FinFET	Chaturvedi, Nitin
2024-10	Design and Analysis of Modified Strong Arm Latch Comparator with Reduced Kickback Noise	Gupta, Anu; Shekhar, Chandra; Chaturvedi, Nitin
2024	Design and implementation of successive approximation register data converter	Gupta, Anu; Chaturvedi, Nitin; Shekhar, Chandra
2020	Design of a Low Power 11T-1MTJ Non-Volatile SRAM Cell with Half-Select Free Operation	Chaturvedi, Nitin
2021	Design of a Low Power Approximate Adder based on Magnetic Tunnel Junction for Image Processing Applications	Chaturvedi, Nitin
2022-12	Design of a Programmable Delay Line with On-Chip Calibration to Achieve Immunity Against Process Variations	Chaturvedi, Nitin
2019	Design of a Robust Logic Gate using Magnetic Tunnel Junction	Chaturvedi, Nitin
2022-08	Design of a STT-MTJ Based Random-Access Memory With In-situ Processing for Data-Intensive Applications	Chaturvedi, Nitin
2023-06	Design of a tunable delay line with on-chip calibration to generate process-invariant PWM signal for in-memory computing	Shenoy, Meetha V.; Chaturvedi, Nitin
2021	Design of an MTJ/CMOS-Based Asynchronous System for Ultra-Low Power Energy Autonomous Applications	Chaturvedi, Nitin
2022	Design of In-Memory Computing Enabled SRAM Macro	Chaturvedi, Nitin
2016	Design of non-volatile asynchronous circuit using CMOS-FDSOI/FinFET technologies	Chaturvedi, Nitin

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