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Browsing by Author Gupta, Anu

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Issue Date	Title	Author(s)
2016-08	Accurate Iris Localization Using Edge Map Generation and Adaptive Circular Hough Transform for Less Constrained Iris Images	Gupta, Anu; Asati, Abhijit
2014	Analysis & implementation of ultra low-power 4-bit CLA in subthreshold regime	Gupta, Anu; Asati, Abhijit
2013	An asynchronous 8-bit 5 MS/s pipelined ADC for biomedical sensor based applications	Gupta, Anu
2012	Asynchronous 8-bit pipelined ADC for self-triggered sensor based applications	Gupta, Anu
2006-07	Automation of clock distribution network design for digital integrated circuits using divide and conquer technique	Gupta, Anu
2013	Characterization of Logical Effort for Improved Delay	Gupta, Anu
2013	CNTFET based design of content addressable memory cells	Gupta, Anu
2013-12	A comparative analysis of power and delay optimise digital logic families for high performance system design	Gupta, Anu
2016	A Comparison of Adiabatic Logic Circuit Techniques for an Energy Efficient 1-Bit Full Adder Design	Gupta, Anu
2018-11	Constant power consumption design of novel differential logic gate for immunity against differential power analysis	Gupta, Anu
2013	Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology	Gupta, Anu
2017	Current-Mode PMOS capacitance multiplier	Gupta, Anu
2022-07	Dedicated hardware architecture for localizing iris in VW images	Asati, Abhijit; Gupta, Anu
2015	Design and ASIC implementation of column compression Wallace/Dadda multiplier in sub-threshold regime	Gupta, Anu; Asati, Abhijit
2002-07-11	Design explorations of VLSI arithmetic circuits	Gupta, Anu
2009	Design of 10-bit Digital to Analog Converter Using Cascaded Operational Amplifier Topology	Gupta, Anu
2009-12	Design of a High Performance, Low Power, Fully Differential Telescopic Cascode Amplifier using Common-Mode Feedback Circuit	Gupta, Anu
2013-08	Design of CNTFET-based 2-bit ternary ALU for nanoelectronics	Gupta, Anu
2012	Design of Logical Effort for Worst Case Power Estimation in a CMOS Circuit in 90 nm Technology	Gupta, Anu
2012	Design of Logical Effort for Worst Case Power Estimation in a CMOS Circuit in 90 nm Technology	Gupta, Anu

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