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Browsing by Author Shekhar, Chandra

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Issue Date	Title	Author(s)
2017-03	Admission Control Policy of Maintenance for Unreliable Server Machining System with Working Vacation	Shekhar, Chandra
2021-07	Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis	Asati, Abhijit; Shekhar, Chandra
2020	Area-optimal FPGA implementation of the YOLO v2 algorithm using High-Level Synthesis	Asati, Abhijit; Shekhar, Chandra
2015-03	Assessment of the Yoga on the Status of the Physical Fitness among Children of the Residential School	Shekhar, Chandra
2016-01	A brief review on retrial queue: Progress in 2010-2015	Shekhar, Chandra
2015-02	Double orbit finite retrial queues with priority customers and service interruptions	Shekhar, Chandra
2009-12	Dual channel addition based FFT processor architecture for signal and image processing	Gupta, Anu; Shekhar, Chandra; Asati, Abhijit
2018	Effect of thickness on the properties of ZnO thin films prepared by reactive RF sputtering	Gupta, Navneet; Kandpal, Kavindra; Shekhar, Chandra
2018-11	Estimation of scattering and intrinsic attenuation based on multiple lapse time window analysis in Sikkim Himalayan region, India	Shekhar, Chandra
2020-04	Fault-tolerant redundant repairable system with different failures and delays	Shekhar, Chandra
2012	Finite Queueing Model with Multitask Servers and Blocking	Shekhar, Chandra
2014	Fuzzy analysis of machine repair problem with switching failure and reboot	Shekhar, Chandra
2014-12	Genome wide analysis as Arabidopsis Thaliana reveals high frequency of AAAGN7CTTT motif	Shekhar, Chandra
2009-05	A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Logic Design Style With Improved Performance	Asati, Abhijit; Shekhar, Chandra
2020-10	High-Level synthesis assisted design and verification framework for automotive radar processors	Asati, Abhijit; Shekhar, Chandra
2020-05	High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications	Asati, Abhijit; Shekhar, Chandra
2008	A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic	Asati, Abhijit; Shekhar, Chandra
2009	A high-speed, hierarchical 16×16 array of array multiplier design	Asati, Abhijit; Shekhar, Chandra
2008	An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style	Asati, Abhijit; Shekhar, Chandra
2020-01	Load sharing redundant repairable systems with switching and reboot delay	Shekhar, Chandra

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