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Browsing by Author Vidhyadharan, Sanjay

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Issue Date	Title	Author(s)
2019-11	An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications	Vidhyadharan, Sanjay
2019-02	Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology	Vidhyadharan, Sanjay
2021-09	CNFET Based Ultra-Low-Power Schmitt Trigger SRAM for Internet of Things (IoT) Applications	Vidhyadharan, Sanjay
2021-02	CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder	Vidhyadharan, Sanjay
2019	An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices	Vidhyadharan, Sanjay
2021-01	An Efficient Ultra-Low-Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices	Vidhyadharan, Sanjay
2023-01	Fast and Low-Power CMOS and CNFET based Hysteresis Voltage Comparator	Vidhyadharan, Sanjay
2021	Gate-Overlap Tunnel Field-Effect Transistors (GOTFETs) for Ultra-Low-Voltage and Ultra-Low-Power VLSI Applications	Vidhyadharan, Sanjay
2021-03	Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications	Vidhyadharan, Sanjay
2020-01	Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node	Vidhyadharan, Sanjay
2020-10	An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger	Vidhyadharan, Sanjay
2021-05	Memristor–CMOS hybrid ultra-low-power high-speed multivibrators	Vidhyadharan, Sanjay
2021-04	Mux Based Ultra-Low-Power Ternary Adders and Multiplier implemented with CNFET and 45 nm MOSFETs	Vidhyadharan, Sanjay
2019-06	A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications	Vidhyadharan, Sanjay
2020-07	Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC	Vidhyadharan, Sanjay
2019	Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications	Vidhyadharan, Sanjay
2021-05	A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM	Vidhyadharan, Sanjay
2020-03	A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder	Vidhyadharan, Sanjay
2019-02	Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology	Vidhyadharan, Sanjay
2020-07	Suppression of Ambipolar Behavior and Simultaneous Improvement in RF Performance of Gate-Overlap Tunnel Field Effect Transistor (GOTFET) Devices	Vidhyadharan, Sanjay

Showing results 1 to 20 of 23 next >