Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node

Abstract

In this paper, four different types of gate-overlap tunnel FET (GOTFET) devices are proposed for ultra-low power applications: (1) generic GOTFETs for digital logic, (2) low- and high-threshold (LVT and HVT) GOTFETs for ternary logic, (3) multi-threshold GOTFETs giving both LVT and HVT characteristics by simply altering their terminal connections and (4) line-tunneling-based GOTFETs for analog applications. The most interesting feature of the proposed GOTFET is that in the same device structure, just by changing the material and doping parameters of the device, we can get the optimal performance for different applications. Each of these GOTFET structures have been optimized such that their characteristics are superior than equally sized 45-nm MOSFETs. Device optimization has been carried out by studying the impact of changes in various device parameters on performance. GOTFET characteristics were simulated using industry-standard synopsys® TCAD tools, while the benchmarking with an equivalent CMOS technology was carried out using the standard 45-nm CMOS library in industry-standard cadence® EDA tool. Proposed GOTFETs have minimum on-state currents Ion at least twice (Ion,GOT≥2Ion,MOS), with maximum off-state currents Ioff remaining at least an order of magnitude lower (Ioff,GOT≤0.1Ioff,MOS), than the corresponding equally sized MOSFETs at the same 45-nm technology node. Circuit analysis and designs are beyond the scope of this paper; however, the innovative GOTFETs proposed in this paper will serve as the basic active devices in digital, ternary logic and analog applications yielding circuit performance far superior to the state-of-the-art designs at the same technology node, as indicated in our previous reports.