An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices

Abstract

Recent studies have indicated that multilogic circuits in VLSI design helps in reducing the transistor count of circuits and increases the data transfer rate significantly. This paper presents an efficient design methodology for the implementation of a two bit ternary output Flash Analog to Digital Converter (ADC) utilizing Tunnel Field Effect Transistors (TFETs). Optimized SiGe TFET structures which have ON currents more than twice while OFF currents at least an order of magnitude lower than the standard 45 nm MOSFETs have been developed. These devices form the basic active elements for the proposed ADC. A new complementary TFET (CTFET) based comparator design is also proposed in the paper which has delays and power consumption lesser than the conventional CMOS based comparator design. An efficient methodology for directly designing logical functions with TFET devices, obtaining 2 bit ternary ADC output with a resolution of 50 mV and input quantized to 9 levels is illustrated in this paper. The proposed CTFET based ADC needs only 48 transistors to encode the comparator outputs to the required 2 bit ternary output which is significantly lower than the transistor count of 70 needed for the 2 bit ternary flash ADC designs available in literature. The performance of the CTFET based ternary ADC has been benchmarked with the same ADC circuit implemented with 45 nm CMOS technology. It has been demonstrated that the CTFET based ADC not only has delays much lesser than the corresponding CMOS based ADC but also consumes significantly lesser power and the overall decrease in Power Delay Product (PDP) has been shown to be 99.7%.