Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications

Abstract

For the first time, innovative low (LVT) and high (HVT) threshold tunnel FET devices have been reported for ternary logic applications. Based on an iterative algorithm, the DG TFET structures have been optimized such that the TFET characteristics are better than the MOSFETs having same width at the standard 45 nm technology node. These devices are designed in such a way that the low and high threshold voltages are VTL = VDD/3 and VTH = 2VDD/3 respectively, with the ranges {0 to VDD/3}, {VDD/3 to 2VDD/3} & {2VDD/3 to VDD} representing the 3 logic states 0, 1 & 2 respectively. Device optimization has been carried out by studying the impact of changes in various device parameters on performance. Optimized TFET devices have been benchmarked with standard CMOS for the same circuit designed using same technology. TFET device characteristics were simulated using Synopsys TCAD tools and circuit performance benchmarking was carried out with the standard 45 nm CMOS library using cadence EDA tool. Proposed LVT & HVT TFETs have ON currents (ION) roughly twice and OFF currents (IOFF) at least an order of magnitude lower than the corresponding MOSFETs. The performance of the optimized TFET based NTI & PTI ternary logic cells have been benchmarked with analogous CMOS circuits at same technology node. The overall Power Delay Products (PDP) of the TFET based logic cells have been demonstrated to be around 99.9% lower than the corresponding CMOS based logic cells. The proposed LVT & HVT TFET based NTI and PTI cells will serve as the starting point for any ternary logic applications.