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Title: | Impact of Thermal Effects on the Performance of the Power Gating Circuits Using NEMS, FinFETs, and NWFETs |
Authors: | Rao, V. Ramgopal |
Keywords: | EEE Berkeley short-channel IGFET model–common multi-gate (BSIM-CMG) FinFET Nano electro-mechanical switches (NEMS) Power gating (PG) |
Issue Date: | May-2021 |
Publisher: | IEEE |
Abstract: | In this article, the power gating (PG) technique is analyzed using nano-electro-mechanical switches (NEMS), FinFETs, and nanowire field-effect transistors (NWFETs). We have used detailed circuit level simulations using well-calibrated models to obtain the conditions for net energy saving with thermal effects. We demonstrate that for a benchmark 17-stage buffer chain circuit, the NEMS PG will be superior to sub-10-nm FinFETs and NWFETs-based gating when the T on / T off ratio is less than 0.1 at room temperature. The ratio increases as temperature increases. Circuit simulations show that the energy gain ( T on / T off = 10 -4 ) due to NEMS gating increases by 3.6 times with reference to NWFETs and 7.3 times as compared to FinFETs-based gating when the temperature increases from 30 °C to 80 °C. NWFETs require a longer breakeven cycle for PG to become more energy-efficient than FinFETs due to its better gate control over the channel. |
URI: | https://ieeexplore.ieee.org/document/9422125 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12550 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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