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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Rao, V. Ramgopal | - |
dc.date.accessioned | 2023-10-20T10:03:09Z | - |
dc.date.available | 2023-10-20T10:03:09Z | - |
dc.date.issued | 2020-07 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/9134391 | - |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12557 | - |
dc.description.abstract | The hot carrier (HC) induced degradation has become a major concern in advanced CMOS technologies because of non-scalable V DD . In this work, we have shown that the HC induced degradation in gate-first HKMG nMOS transistors can be modulated by optimizing the device width, lanthanum capping layer thickness, and pre-gate carbon (C) implant. The physics responsible for these observations are investigated and attributed to the reduction in the number of defects (traps) in hafnium oxide (HfO 2 ) and reduction in carrier injection into these defects. It is also shown that the HC performance of these transistors could be further improved by increasing the active-to-active spacing. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.subject | EEE | en_US |
dc.subject | Device scaling | en_US |
dc.subject | Channel width | en_US |
dc.subject | Gate current | en_US |
dc.subject | Lanthanum (La) capping layer | en_US |
dc.subject | Dipole | en_US |
dc.subject | Threshold voltage | en_US |
dc.title | Effect of Device Dimensions, Layout and Pre-Gate Carbon Implant on Hot Carrier Induced Degradation in HKMG nMOS Transistors | en_US |
dc.type | Article | en_US |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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