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dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-10-20T10:03:09Z-
dc.date.available2023-10-20T10:03:09Z-
dc.date.issued2020-07-
dc.identifier.urihttps://ieeexplore.ieee.org/document/9134391-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12557-
dc.description.abstractThe hot carrier (HC) induced degradation has become a major concern in advanced CMOS technologies because of non-scalable V DD . In this work, we have shown that the HC induced degradation in gate-first HKMG nMOS transistors can be modulated by optimizing the device width, lanthanum capping layer thickness, and pre-gate carbon (C) implant. The physics responsible for these observations are investigated and attributed to the reduction in the number of defects (traps) in hafnium oxide (HfO 2 ) and reduction in carrier injection into these defects. It is also shown that the HC performance of these transistors could be further improved by increasing the active-to-active spacing.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectDevice scalingen_US
dc.subjectChannel widthen_US
dc.subjectGate currenten_US
dc.subjectLanthanum (La) capping layeren_US
dc.subjectDipoleen_US
dc.subjectThreshold voltageen_US
dc.titleEffect of Device Dimensions, Layout and Pre-Gate Carbon Implant on Hot Carrier Induced Degradation in HKMG nMOS Transistorsen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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