Please use this identifier to cite or link to this item:
http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12567
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Rao, V. Ramgopal | - |
dc.date.accessioned | 2023-10-21T05:17:59Z | - |
dc.date.available | 2023-10-21T05:17:59Z | - |
dc.date.issued | 2019-10 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/8798755 | - |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12567 | - |
dc.description.abstract | On substrates such as Ge, GaAs, GaSb, InP and a few other materials, Fermi-level pinning (FLP) is a major concern as it inhibits barrier height modulation (BHM) with different work function metals. We demonstrate for the first time a novel and simple mechanical exfoliation of multilayer black phosphorus (BP) as an interfacial layer (IL) to depin the Fermi level on Ge substrate. Multilayer-BP IL was able to alleviate the critical issue of FLP, as it leads to (i) an increase in reverse current by more than two and a half orders on n-Ge (quasi-Ohmic current-voltage(I-V) characteristics) with a decrease in Schottky barrier height (SBH) of 0.14 eV, and (ii) a decrease in reverse current by two orders on p-Ge (Schottky I-V characteristics) with an increase in SBH of 0.52 eV as compared to devices without IL. The device with multilayer-WSe2 IL, having a high conduction band offset (CBO), leads to poor electrical performance compared to a multilayer-BP IL with low CBO. Based on this study, multilayer-BP can be considered as an ideal candidate for an IL material to resolve FLP issue and achieve BHM for various other pinned semiconductors as well. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.subject | EEE | en_US |
dc.subject | Germanium (Ge) | en_US |
dc.subject | Black phosphorus (BP) | en_US |
dc.subject | Fermi-level pinning | en_US |
dc.subject | Tungsten diselenide (WSe₂) | en_US |
dc.title | Fermi-Level Depinning in Germanium Using Black Phosphorus as an Interfacial Layer | en_US |
dc.type | Article | en_US |
Appears in Collections: | Department of Electrical and Electronics Engineering |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.