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Title: | A Nano-Electro-Mechanical Switch Based Power Gating for Effective Stand-by Power Reduction in FinFET Technologies |
Authors: | Rao, V. Ramgopal |
Keywords: | EEE NEMS Power gating (PG) FinFET Berkeley short-channel IGFET model–common multi-gate (BSIM-CMG) |
Issue Date: | May-2017 |
Publisher: | IEEE |
Abstract: | In this letter, we show that using the experimentally demonstrated nano-electro-mechanical-switches (NEMS) and our design methodology, the standby power dissipation can be reduced to negligible levels in 14-nm bulk FinFET technologies. Using two realistic NEMS structures, demonstrated in the literature for power gating applications, a design window is derived for achieving the targeted specifications without compromising on the performance and area. Cantilever NEMS requires less area as compared with the suspended NEMS, but reliability is a concern. We demonstrate that for a 17-stage ring oscillator circuit, the NEMS power gating will perform better than the FinFET-based power gating when the T ON /T OFF ratio is less than 0.002. |
URI: | https://ieeexplore.ieee.org/document/7885519 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12587 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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