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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12587
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dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-10-23T04:08:41Z-
dc.date.available2023-10-23T04:08:41Z-
dc.date.issued2017-05-
dc.identifier.urihttps://ieeexplore.ieee.org/document/7885519-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12587-
dc.description.abstractIn this letter, we show that using the experimentally demonstrated nano-electro-mechanical-switches (NEMS) and our design methodology, the standby power dissipation can be reduced to negligible levels in 14-nm bulk FinFET technologies. Using two realistic NEMS structures, demonstrated in the literature for power gating applications, a design window is derived for achieving the targeted specifications without compromising on the performance and area. Cantilever NEMS requires less area as compared with the suspended NEMS, but reliability is a concern. We demonstrate that for a 17-stage ring oscillator circuit, the NEMS power gating will perform better than the FinFET-based power gating when the T ON /T OFF ratio is less than 0.002.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectNEMSen_US
dc.subjectPower gating (PG)en_US
dc.subjectFinFETen_US
dc.subjectBerkeley short-channel IGFET model–common multi-gate (BSIM-CMG)en_US
dc.titleA Nano-Electro-Mechanical Switch Based Power Gating for Effective Stand-by Power Reduction in FinFET Technologiesen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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