Please use this identifier to cite or link to this item:
http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12590
Title: | Considerations for Static Energy Reduction in Digital CMOS ICs Using NEMS Power Gating |
Authors: | Rao, V. Ramgopal |
Keywords: | EEE FinFET Hybrid FinFET+NEMS Leakage current NEMS switches Static energy reduction |
Issue Date: | Mar-2017 |
Publisher: | IEEE |
Abstract: | Due to its infinite OFF resistance, Nano-Electro-Mechanical Switches (NEMS) have been recently proposed to reduce leakage current during the standby mode in large-scale Digital ICs in nano regime area. However, detailed analysis of the conditions at which the NEMS devices will have impact is missing. In this brief, the technique of power gating is analyzed with a NEMS switch using detailed circuit level simulations to obtain the conditions under which one can obtain net energy savings as compared with FinFET-based power gating. Finally, applicability in the energy reduction on a futuristic system-on-chip for mobile platform made using 14 nm gate length FinFET device is evaluated. |
URI: | https://ieeexplore.ieee.org/document/7842575 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12590 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.