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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Rao, V. Ramgopal | - |
dc.date.accessioned | 2023-10-23T10:54:55Z | - |
dc.date.available | 2023-10-23T10:54:55Z | - |
dc.date.issued | 2016-03 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/7374720 | - |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12604 | - |
dc.description.abstract | In this paper, we present a variability-aware 3-D mixed-mode device simulation study of Si gate-all-around (GAA) nanowire MOSFET (NWFET)-based 6-T static random access memory (SRAM) bit-cell stability and performance considering metal-gate granularity (MGG) induced intrinsic device random fluctuations and quantum corrected room temperature drift-diffusion transport. The impact of MGG contributed intrinsic variability on Si GAA n- and p-NWFETs-based SRAM cell static noise margins (SNM), write and read delay time are statistically analyzed. Our statistical simulations predict acceptable stability for the Si NWFET 6-T SRAM cell with V DD downscaling up to 0.5 V. The simulation estimated mean hold SNM values follow a lowering trend with V DD downscaling, similar to the hold SNM experimental data reported in the literature for Si GAA NWFET-based SRAM arrays. We further show a linear variation in statistical variance of hold SNM with gate metal grain size and work function. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.subject | EEE | en_US |
dc.subject | Gate-all-around | en_US |
dc.subject | Metal gate granularity | en_US |
dc.subject | Silicon nanowire FET | en_US |
dc.subject | SRAM | en_US |
dc.subject | Work function | en_US |
dc.title | Effect of Metal Gate Granularity Induced Random Fluctuations on Si Gate-All-Around Nanowire MOSFET 6-T SRAM Cell Stability | en_US |
dc.type | Article | en_US |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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