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Title: | High-Voltage MOS Device Design for Improved Static and RF Performance |
Authors: | Rao, V. Ramgopal |
Keywords: | EEE DePMOS Device CMOS technologies |
Issue Date: | Oct-2015 |
Publisher: | IEEE |
Abstract: | In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in RON and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device. |
URI: | https://ieeexplore.ieee.org/document/7247702 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12612 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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