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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12612
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dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-10-25T06:30:26Z-
dc.date.available2023-10-25T06:30:26Z-
dc.date.issued2015-10-
dc.identifier.urihttps://ieeexplore.ieee.org/document/7247702-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12612-
dc.description.abstractIn this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in RON and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectDePMOS Deviceen_US
dc.subjectCMOS technologiesen_US
dc.titleHigh-Voltage MOS Device Design for Improved Static and RF Performanceen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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