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Title: | A Fully Integrated RF PA in 28nm CMOS with Device Design for Optimized Performance and ESD Robustness |
Authors: | Rao, V. Ramgopal |
Keywords: | EEE CMOS technologies Device-circuit codesign Electrostatic discharge (ESD) System-on-chip (SoC) Shallow-trench-isolation (STI) |
Issue Date: | Sep-2015 |
Publisher: | IEEE |
Abstract: | In this paper, we report drain-extended MOS device design guidelines for the RF power amplifier (RF PA) applications. A complete RF PA circuit in a 28-nm CMOS technology node with the matching and biasing network is used as a test vehicle to validate the RF performance improvement by a systematic device design. A complete RF PA with 0.16-W/mm power density is reported experimentally. By simultaneous improvement of device-circuit performance, 45% improvement in the circuit RF power gain, 25% improvement in the power-added efficiency at 1-GHz frequency, and 5× improvement in the electrostatic discharge robustness are reported experimentally. |
URI: | https://ieeexplore.ieee.org/abstract/document/7258333 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12614 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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