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dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-10-26T07:08:54Z-
dc.date.available2023-10-26T07:08:54Z-
dc.date.issued2013-12-
dc.identifier.urihttps://ieeexplore.ieee.org/document/6658861-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12637-
dc.description.abstractThe role of trap-assisted tunneling (TAT) in the degradation of the subthreshold swing (SS) in n-type line tunnel field-effect transistors (TFETs) is investigated through the experiments and simulations. A two to fourfold increase in the interface state density is achieved by applying a positive or a negative stress between the gate and the source. The negative stress shows no impact on the SS in spite of nearly fourfold increase in the interface state density. A nearly twofold increase in interface state density and improvement in SS are observed under the application of positive stress. The improvement in SS is attributed to H + species released from the Si/ SiO2 interface during stress, which moves toward the bulk Si, passivating boron and bulk Si traps, thereby improving the SS. Under negative stress bias, the released H + species drifts toward the gate electrode, and hence no change in SS was observed. These experiments suggest that the SS degradation is mainly caused by TAT through bulk Si traps and insensitive to interface traps. A good control of bulk semiconductor trap density will be required to achieve sub-60-mV/decade SS in line TFETs.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectBias stress measurementsen_US
dc.subjectBulk trapsen_US
dc.subjectCharacterizationen_US
dc.subjectFabricationen_US
dc.subjectInterface trapsen_US
dc.subjectTrap-assisted tunneling (TAT)en_US
dc.subjectTunnel field effect transistor (TFET)en_US
dc.titleInvestigation of Subthreshold Swing in Line Tunnel FETs Using Bias Stress Measurementsen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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