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http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12647Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Rao, V. Ramgopal | - |
| dc.date.accessioned | 2023-10-26T10:08:52Z | - |
| dc.date.available | 2023-10-26T10:08:52Z | - |
| dc.date.issued | 2012-10 | - |
| dc.identifier.uri | https://ieeexplore.ieee.org/abstract/document/6269049 | - |
| dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12647 | - |
| dc.description.abstract | A novel drain-extended FinFET device is proposed in this letter for high-voltage and high-speed applications. A 2 × better R ON versus V BD tradeoff is shown from technology computer-aided design simulations for the proposed device, when compared with a conventional device option. Moreover, a device design and optimization guideline has been provided for the proposed device. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | IEEE | en_US |
| dc.subject | EEE | en_US |
| dc.subject | Drain extended MOSFET (DeMOS) | en_US |
| dc.subject | FinFET | en_US |
| dc.subject | High voltage (HV) | en_US |
| dc.subject | System-on-a-chip (SoC) | en_US |
| dc.title | A Novel Drain-Extended FinFET Device for High-Voltage High-Speed Applications | en_US |
| dc.type | Article | en_US |
| Appears in Collections: | Department of Electrical and Electronics Engineering | |
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