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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Rao, V. Ramgopal | - |
dc.date.accessioned | 2023-10-27T03:50:39Z | - |
dc.date.available | 2023-10-27T03:50:39Z | - |
dc.date.issued | 2012-05 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/abstract/document/6166392 | - |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12656 | - |
dc.description.abstract | We report on the thermal failure of fin-shaped field-effect transistor (FinFET) devices under the normal operating condition. Pre- and post failure characteristics are investigated. A detailed physical insight on the lattice heating and heat flux in a 3-D front end of the line and complex back end of line-of a logic circuit network-is given for bulk/silicon-on-insulator (SOI) FinFET and extremely thin SOI devices using 3-D TCAD. Moreover, the self-heating behavior of both the planar and nonplanar devices is compared. Even bulk FinFET shows critical self-heating. Layout, device, and technology design guidelines (based on complex 3-D TCAD) are given for a robust on-chip thermal management. Finally, an improved framework is proposed for an accurate electrothermal modeling of various FinFET device architectures by taking into account all major heat flux paths. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.subject | EEE | en_US |
dc.subject | BEOL reliability | en_US |
dc.subject | Electrothermal modeling | en_US |
dc.subject | Electrostatic discharge (ESD) | en_US |
dc.subject | Extremely thin silicon on insulator (SOI) (ETSOI) | en_US |
dc.subject | Fin-shaped field-effect transistor (FET) (FinFET) | en_US |
dc.title | Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures | en_US |
dc.type | Article | en_US |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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