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Title: | A new physical insight and 3D device modeling of STI type denmos device failure under ESD conditions |
Authors: | Rao, V. Ramgopal |
Keywords: | EEE Electrostatic discharge (ESD) Protection CMOS technology Space charge CMOS process Space technology Power dissipation Circuit simulation |
Issue Date: | 2009 |
Publisher: | IEEE |
Abstract: | We present experimental and simulation studies of STI type DeNMOS devices under ESD conditions. The impact of base-push-out, power dissipation because of space charge build-up and, regenerative NPN action, on the various phases of filamentation and the final thermal runaway is discussed. A modification of the device layout is proposed to achieve an improvement (~2X) in failure threshold (I T2 ). |
URI: | https://ieeexplore.ieee.org/document/5173327 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12681 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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