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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12685
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dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-10-27T11:04:44Z-
dc.date.available2023-10-27T11:04:44Z-
dc.date.issued2010-06-
dc.identifier.urihttps://ieeexplore.ieee.org/abstract/document/5446394-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12685-
dc.description.abstractFor the first time, we propose a novel bottom spacer fin-shaped field-effect-transistor (FinFET) structure for logic applications suitable for system-on-chip (SoC) requirements. The proposed device achieved improved short-channel, power-delay, and self-heating performance compared with standard silicon-on-insulator FinFETs. Process aspects of the proposed device are also discussed in this paper. Physical insight into the improvement toward the short-channel performance and power dissipation is given through a detailed 3-D device/mixed-mode simulation. The self-heating behavior of the proposed device is compared with standard FinFETs by using detailed electrothermal simulations. The proposed device requires an extra process step but enables smaller electrical width for self-loaded circuits and is an excellent option for SoC applications.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectBulk fin-shaped field-effect transistor (FinFET)en_US
dc.subjectElectrothermal modelingen_US
dc.subjectFin-shaped field-effect transistor (FET) (FinFET)en_US
dc.subjectWidth quantizationen_US
dc.titleA Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performanceen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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