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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12688
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dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-10-27T11:12:54Z-
dc.date.available2023-10-27T11:12:54Z-
dc.date.issued2010-10-
dc.identifier.urihttps://www.sciencedirect.com/science/article/abs/pii/S0167931709008569-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12688-
dc.description.abstractIn this paper, we report a study to understand the fin width dependence on performance, variability and reliability of n-type and p-type triple-gate fin field effect transistors (FinFETs) with high-k dielectric and metal gate. Our results indicate that with decreasing fin width the well-known performance improvement in terms of sub-threshold swing and drain-induced barrier lowering are accompanied by a degradation of the variability and the reliability. As a matter of fact fin width scaling causes (i) higher hot-carrier degradation (HC) in nFinFETs owing to the higher charge carrier temperature for the same internal stress voltages; (ii) worse negative bias temperature instability (NBTI) in pFinFETs due to the increased contribution from the (1 1 0) surface; (iii) higher variability due to the non-uniform fin extension doping, as highlighted by applying a novel characterization technique.en_US
dc.language.isoenen_US
dc.publisherElsevieren_US
dc.subjectEEEen_US
dc.subjectFinFETsen_US
dc.titleImplications of fin width scaling on variability and reliability of high-k metal gate FinFETsen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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