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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/12702
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dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-10-28T06:45:23Z-
dc.date.available2023-10-28T06:45:23Z-
dc.date.issued2009-06-
dc.identifier.urihttps://ieeexplore.ieee.org/document/4812005-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12702-
dc.description.abstractIn this paper, we investigate the quality of MOSFET gate stacks where high- k materials are implemented as gate dielectrics. We evaluate both drain- and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high- k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/ f noise point of view.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectDrain noiseen_US
dc.subjectGate noiseen_US
dc.subjectMOSFETsen_US
dc.subject1/f noiseen_US
dc.title1/f Noise in Drain and Gate Current of MOSFETs With High-k Gate Stacks Publisher: IEEE PDFen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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