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Title: | Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization |
Authors: | Rao, V. Ramgopal |
Keywords: | EEE CMOS scaling FinFET Fringe-induced barrier lowering (GFIBL) Short-channel effects (SCEs) |
Issue Date: | Jan-2008 |
Publisher: | IEEE |
Abstract: | The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate underlap regions as the technology scales down. We present a phenomenon called the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions. In these FinFETs, we show that the GFIBL can be effectively used to improve I on . We propose the use of high-kappa spacers in such FinFETs to enhance the effect of GFIBL and thereby achieve better device and circuit performance. When compared with the underlap FinFETs with Si 3 N 4 spacers, with kappa=20 spacers, we show that it is possible to achieve an 80% increase in I on at iso-I off conditions and a 15% decrease in the inverter delay for a fan-out of four. |
URI: | https://ieeexplore.ieee.org/document/4408750 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12712 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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