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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Rao, V. Ramgopal | - |
dc.date.accessioned | 2023-10-30T06:24:06Z | - |
dc.date.available | 2023-10-30T06:24:06Z | - |
dc.date.issued | 2008-01 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/4408750 | - |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12712 | - |
dc.description.abstract | The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate underlap regions as the technology scales down. We present a phenomenon called the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions. In these FinFETs, we show that the GFIBL can be effectively used to improve I on . We propose the use of high-kappa spacers in such FinFETs to enhance the effect of GFIBL and thereby achieve better device and circuit performance. When compared with the underlap FinFETs with Si 3 N 4 spacers, with kappa=20 spacers, we show that it is possible to achieve an 80% increase in I on at iso-I off conditions and a 15% decrease in the inverter delay for a fan-out of four. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.subject | EEE | en_US |
dc.subject | CMOS scaling | en_US |
dc.subject | FinFET | en_US |
dc.subject | Fringe-induced barrier lowering (GFIBL) | en_US |
dc.subject | Short-channel effects (SCEs) | en_US |
dc.title | Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization | en_US |
dc.type | Article | en_US |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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