![DSpace logo](/jspui/image/logo.gif)
Please use this identifier to cite or link to this item:
http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12713
Title: | Electret mechanism, hysteresis, and ambient performance of sol-gel silica gate dielectrics in pentacene field-effect transistors |
Authors: | Rao, V. Ramgopal |
Keywords: | EEE Hysteresis Dielectrics Electret mechanism |
Issue Date: | Dec-2007 |
Publisher: | IEEE |
Abstract: | The electret induced hysteresis was studied in sol-gel silica films that result in higher drain currents and improved device performance in pentacene field-effect transistors. Vacuum and ambient condition studies of the hysteresis behavior and capacitance-voltage characteristics on single layer and varying thicknesses of bilayer dielectrics confirmed that blocking layers of thermal oxide could effectively eliminate the electret induced hysteresis, and that thin (25nm) sol-gel silica dielectrics enabled elimination of nanopores thus realizing stable device characteristics under ambient conditions. |
URI: | https://pubs.aip.org/aip/apl/article/91/24/242107/237568/Electret-mechanism-hysteresis-and-ambient http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12713 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.