Border-Trap Characterization in High-κ Strained-Si MOSFETs

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DC Field	Value	Language
dc.contributor.author	Rao, V. Ramgopal	-
dc.date.accessioned	2023-10-30T06:43:01Z	-
dc.date.available	2023-10-30T06:43:01Z	-
dc.date.issued	2007-08	-
dc.identifier.uri	https://ieeexplore.ieee.org/document/4278369	-
dc.identifier.uri	http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12716	-
dc.description.abstract	In this letter, we focus on the border-trap characterization of TaN/HfO 2 /Si and TaN/HfO 2 /strained-Si/Si 0.8 Ge 0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-kappa films on strained- Si/Si 0.8 Ge 0.2 .These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-kappa films on strained-Si are also proposed.	en_US
dc.language.iso	en	en_US
dc.publisher	IEEE	en_US
dc.subject	EEE	en_US
dc.subject	Border traps	en_US
dc.subject	Charge pumping	en_US
dc.subject	Hysteresis	en_US
dc.subject	Interface trapping	en_US
dc.subject	Strained-Si	en_US
dc.subject	1/f noise	en_US
dc.title	Border-Trap Characterization in High-κ Strained-Si MOSFETs	en_US
dc.type	Article	en_US
Appears in Collections:	Department of Electrical and Electronics Engineering

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