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http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12716| Title: | Border-Trap Characterization in High-κ Strained-Si MOSFETs |
| Authors: | Rao, V. Ramgopal |
| Keywords: | EEE Border traps Charge pumping Hysteresis Interface trapping Strained-Si 1/f noise |
| Issue Date: | Aug-2007 |
| Publisher: | IEEE |
| Abstract: | In this letter, we focus on the border-trap characterization of TaN/HfO 2 /Si and TaN/HfO 2 /strained-Si/Si 0.8 Ge 0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-kappa films on strained- Si/Si 0.8 Ge 0.2 .These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-kappa films on strained-Si are also proposed. |
| URI: | https://ieeexplore.ieee.org/document/4278369 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12716 |
| Appears in Collections: | Department of Electrical and Electronics Engineering |
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