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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Rao, V. Ramgopal | - |
dc.date.accessioned | 2023-10-30T06:54:46Z | - |
dc.date.available | 2023-10-30T06:54:46Z | - |
dc.date.issued | 2007 | - |
dc.identifier.uri | https://search.ieice.org/bin/summary.php?id=e90-c_10_2051&category=C&year=2007&lang=E&abst= | - |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12717 | - |
dc.description.abstract | In this paper, we have systematically investigated parasitic effects due to the gate and source-drain engineering in multi-gate transistors. The potential impact of high-K dielectrics on multi-gate MOSFETs (MuGFETs), such as FinFET, is evaluated through 2D and 3D device simulations over a wide range of proposed dielectric values. It is observed that introduction of high-K dielectrics will significantly degrade the short channel effects (SCEs), however a combination of oxide and high-K stack can effectively control this degradation. The degradation is mainly due to the increase in the internal fringe capacitance coupled with the decrease in gate-channel capacitance. From the circuit perspective, an optimum K value has been identified through mixed mode simulations. Further, as a part of this work, the importance of optimization of the shape of the spacer region is highlighted through full 3D simulations. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEICE | en_US |
dc.subject | EEE | en_US |
dc.subject | Multi-gate | en_US |
dc.subject | Fin-FETs | en_US |
dc.subject | High-K dielectric | en_US |
dc.subject | Fringe capacitance | en_US |
dc.subject | Parasitic effect | en_US |
dc.title | Parasitic effects in multi-gate MOSFETs | en_US |
dc.type | Article | en_US |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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