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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Rao, V. Ramgopal | - |
dc.date.accessioned | 2023-10-30T07:01:39Z | - |
dc.date.available | 2023-10-30T07:01:39Z | - |
dc.date.issued | 2007-04 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/4137641 | - |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12718 | - |
dc.description.abstract | The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C of in addition to an increase in the internal fringe capacitance C if with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.subject | EEE | en_US |
dc.subject | Fin field-effect transistors (FinFETs) | en_US |
dc.subject | Fringing-induced barrier lowering (FIBL) | en_US |
dc.subject | Short-channel effects (SCEs) | en_US |
dc.subject | Noise margin | en_US |
dc.title | Impact of High-k Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs | en_US |
dc.type | Article | en_US |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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