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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Rao, V. Ramgopal | - |
dc.date.accessioned | 2023-10-30T10:03:43Z | - |
dc.date.available | 2023-10-30T10:03:43Z | - |
dc.date.issued | 2005-07 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/1459125 | - |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12730 | - |
dc.description.abstract | Lateral asymmetric channel (LAC) or single halo devices have been reported to exhibit excellent short channel behavior in the sub-100-nm regime. In this paper, we have quantified the performance degradation in LAC devices due to fingered layouts. Our mixed-mode two-dimensional simulation results show that though the fingered layout of the device limits the performance of these MOSFETs, they still show superior performance over the conventional devices in the sub-100-nm channel length regime. We also present the simulation results of a two-stage operational amplifier with LAC and conventional devices using a 0.13-/spl mu/m technology with the help of look-up table simulations. Our results show that for the given design specifications, an OPAMP layout with conventional devices occupies 18% more chip area compared to the LAC device. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.subject | EEE | en_US |
dc.subject | Analog circuit | en_US |
dc.subject | Channel engineering | en_US |
dc.subject | Lateral asymmetric channel (LAC) | en_US |
dc.subject | Quasi-static | en_US |
dc.subject | Look-up table (LUT) | en_US |
dc.title | Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs | en_US |
dc.type | Article | en_US |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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