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Title: | Silicon film thickness optimization for SOI-DTMOS from circuit performance considerations |
Authors: | Rao, V. Ramgopal |
Keywords: | EEE Semiconductor films Circuit optimization Silicon-on-insulator technology Capacitance Immune system Delay effects MOSFET circuits CMOS technology Circuit simulation |
Issue Date: | Jun-2004 |
Publisher: | IEEE |
Abstract: | The performance of partially depleted silicon-on-insulator (PDSOI) dynamic threshold MOSFET (DTMOS) devices is degraded by the body capacitance and body resistance, which depend strongly on the silicon film thickness. We show that the body RC time constant reduces up to a certain value of silicon film thickness, and then saturates. However, delay of a DTMOS circuit is affected not only by the RC delay of the body but also by the additional load capacitance, which appears due to the gate to body contact. In this paper, we propose a model for PDSOI-DTMOS circuit delay, taking the effect of body parasitics into account, and use it to study the circuit delay as a function of silicon film thickness. Using this model, we show that the optimum value of silicon film thickness is approximately equal to the depletion width in the silicon film in a typical sub-100-nm PDSOI-DTMOS technology. |
URI: | https://ieeexplore.ieee.org/abstract/document/1302251 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12736 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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