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dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-10-31T05:54:48Z-
dc.date.available2023-10-31T05:54:48Z-
dc.date.issued2003-12-
dc.identifier.urihttps://ieeexplore.ieee.org/document/1255612-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12744-
dc.description.abstractIn this paper, we have systematically investigated the effect of scaling on analog performance parameters in lateral asymmetric channel (LAC) MOSFETs and compared their performance with conventional (CON) MOSFETs for mixed-signal applications. Our results show that, in LAC MOSFETs, there is significant improvement in the intrinsic device performance for analog applications (such as device gain, gm/I/sub D/ etc.) down to the 70-nm technology node, in addition to an improvement in drive current and other parameters over a wide range of channel lengths. A systematic comparison on the performance of amplifiers and CMOS inverters with CON and LAC MOSFETs is also performed. The tradeoff between power dissipation and device performance is explored with detailed circuit simulations for both CON and LAC MOSFETs.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectMOSFETsen_US
dc.subjectSemiconductor device dopingen_US
dc.subjectMixed analog-digital integrated circuitsen_US
dc.subjectCMOS integrated circuitsen_US
dc.titleImpact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performanceen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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