DSpace logo

  1. BITS Pilani Institutional Repository
  2. BITS Faculty Publications
  3. Department of Electrical and Electronics Engineering
Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/12746
Full metadata record
DC FieldValueLanguage
dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-10-31T06:05:54Z-
dc.date.available2023-10-31T06:05:54Z-
dc.date.issued2001-07-
dc.identifier.urihttps://ieeexplore.ieee.org/document/941497-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12746-
dc.description.abstractIn this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) and conventional homogeneously doped channel (uniform) SOI MOSFETs using a novel gate-induced-drain-leakage (GIDL) current technique. The parasitic bipolar current gain /spl beta/ has been experimentally measured for LAC and uniform SOI MOSFETs using the GIDL current technique. The lower parasitic bipolar current gain observed in LAC SOI MOSFETs is explained with the help of 2D device simulations.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectTransistorsen_US
dc.subjectMOSFETsen_US
dc.subjectLos Angeles Councilen_US
dc.subjectTunnelingen_US
dc.subjectLeakage currenten_US
dc.subjectCurrent measurementen_US
dc.subjectGain measurementen_US
dc.subjectSemiconductor filmsen_US
dc.titleAnalysis of floating body effects in thin film SOI MOSFETs using the GIDL current techniqueen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

Files in This Item:
There are no files associated with this item.
Show simple item record


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.