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http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/12747Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Rao, V. Ramgopal | - |
| dc.date.accessioned | 2023-10-31T06:14:40Z | - |
| dc.date.available | 2023-10-31T06:14:40Z | - |
| dc.date.issued | 2001-07 | - |
| dc.identifier.uri | https://ieeexplore.ieee.org/document/941497 | - |
| dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12747 | - |
| dc.description.abstract | In this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) and conventional homogeneously doped channel (uniform) SOI MOSFETs using a novel gate-induced-drain-leakage (GIDL) current technique. The parasitic bipolar current gain /spl beta/ has been experimentally measured for LAC and uniform SOI MOSFETs using the GIDL current technique. The lower parasitic bipolar current gain observed in LAC SOI MOSFETs is explained with the help of 2D device simulations. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | IEEE | en_US |
| dc.subject | EEE | en_US |
| dc.subject | Transistors | en_US |
| dc.subject | MOSFETs | en_US |
| dc.subject | Los Angeles Council | en_US |
| dc.subject | Tunneling | en_US |
| dc.subject | Leakage current | en_US |
| dc.subject | Current measurement | en_US |
| dc.subject | Low voltage | en_US |
| dc.subject | CMOS technology | en_US |
| dc.title | Analysis of Floating Body Effects in Thin Film Conventional and Single Pocket SOI MOSFETs using the GIDL Current Technique | en_US |
| dc.type | Article | en_US |
| Appears in Collections: | Department of Electrical and Electronics Engineering | |
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