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dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-10-31T06:34:48Z-
dc.date.available2023-10-31T06:34:48Z-
dc.date.issued2001-04-
dc.identifier.urihttps://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=915686-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12751-
dc.description.abstractMetal–nitride–semiconductor FETs (MNSFETs) having channel lengths down to 100 nm and a novel jet vapor deposited (JVD) Si3N4 gate dielectric have been fabricated and characterized. When compared with MOSFETs having a thermal SiO2 gate insulator, the MNSFETs show a comparable drain current drive, transconductance, subthreshold slope and pre-stress interface quality. A novel charge pumping technique is employed to characterize the hot-carrier induced interface-trap generation in MNSFETs and MOSFETs. Under identical substrate current during stress, MNSFETs show less interface-state generation and drain current degradation, for various channel lengths, stress times and supply voltages, despite the fact that the Si-Si3N4 barrier (2.1 eV) is lower than the Si-SiO2 barrier (3.1 eV). The time and voltage dependence of hot-carrier degradation has been found to be distinctly different for MNSFETs compared to SiO2 MOSFETs.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectCharge pumpingen_US
dc.subjectHot-carrier effecten_US
dc.subjectJet vapor deposition (JVD)en_US
dc.subjectMOSFETsen_US
dc.subjectSilicon nitrideen_US
dc.titlePerformance and Hot-Carrier Reliability of 100 nm Channel Length Jet Vapor Deposited Si3N4 MNSFETsen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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