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Title: | Sub-100 nm CMOS circuit performance with high-K gate dielectrics |
Authors: | Rao, V. Ramgopal |
Keywords: | EEE CMOS integrated circuits High-K gate dielectrics |
Issue Date: | Jul-2001 |
Publisher: | Elsevier |
Abstract: | In this paper we look at the effect of fringing fields on the circuit performance by use of high permittivity (K) gate dielectrics in 70 nm CMOS technologies, from Monte-Carlo and mixed-mode simulations. Our results clearly show a decrease in the external fringing capacitance and an increase in the internal fringing capacitance, when the conventional SiO2 is replaced by high-K gate dielectrics. It also indicates an optimum K value for a given technology generation in terms of circuit and device short-channel performance. |
URI: | https://www.sciencedirect.com/science/article/abs/pii/S0026271401000683 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12753 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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