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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12767
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dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-10-31T09:24:11Z-
dc.date.available2023-10-31T09:24:11Z-
dc.date.issued1998-05-
dc.identifier.urihttps://ieeexplore.ieee.org/document/670162-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12767-
dc.description.abstractIn this paper, we describe the application of gate-induced-drain-leakage (GIDL) current for the characterization of gate edge damage which occurs during the plasma etch processes. We show from experimental and simulation results that when the channel is biased in accumulation and with the drain-substrate junction reverse biased, charge injection is localized in the gate-drain overlap region. Under this localized charge injection (LCI) mode of operation, the gate voltage is a function of edge oxide thickness which in turn can be related to the plasma damage received during the poly-etch and subsequent spacer oxide formation. The detailed mechanism of localized charge injection for a study of plasma edge damage is explained along with the experimental demonstration of this technique using submicron MOSFET's.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectPlasma applicationsen_US
dc.subjectPlasma materials processingen_US
dc.subjectPlasma devicesen_US
dc.subjectPlasma simulationen_US
dc.subjectEtchingen_US
dc.subjectElectron trapsen_US
dc.titleCharge injection using gate-induced-drain-leakage current for characterization of plasma edge damage in CMOS devicesen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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