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Title: | Hysteresis behavior in 85-nm channel length vertical n-MOSFETs grown by MBE |
Authors: | Rao, V. Ramgopal |
Keywords: | EEE Hysteresis MOSFET circuits Electrons Plasma temperature Impact ionization Voltage control |
Issue Date: | Jun-1996 |
Publisher: | IEEE |
Abstract: | Vertical n-MOSFETs with channel lengths of 85 nm have been grown by MBE. For drain-to-source voltages V/sub DS/>3.3 V, these transistors exhibit hysteresis behavior similar to the reported behavior of fully depleted SOI-MOSFETs. Our results also show a gate voltage controlled turn-off of the drain current when the transistor is operating in the hysteresis mode. We have analyzed this behavior in vertical n-MOSFETs using 2-D device simulation and our results show a threshold value for the hole concentration across the source-channel junction which is required for the forward biasing of this junction. For a transistor operating in the hysteresis mode, we show that the potential barrier height for electron injection across the source-channel junction increases for increasing negative gate voltages during retrace. This results in a gate controlled turn-off of the drain current for SOI and vertical n-MOSFETs operating in the regenerative mode. |
URI: | https://ieeexplore.ieee.org/document/502132 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12772 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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