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dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-10-31T10:56:54Z-
dc.date.available2023-10-31T10:56:54Z-
dc.date.issued1996-06-
dc.identifier.urihttps://ieeexplore.ieee.org/document/502132-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12772-
dc.description.abstractVertical n-MOSFETs with channel lengths of 85 nm have been grown by MBE. For drain-to-source voltages V/sub DS/>3.3 V, these transistors exhibit hysteresis behavior similar to the reported behavior of fully depleted SOI-MOSFETs. Our results also show a gate voltage controlled turn-off of the drain current when the transistor is operating in the hysteresis mode. We have analyzed this behavior in vertical n-MOSFETs using 2-D device simulation and our results show a threshold value for the hole concentration across the source-channel junction which is required for the forward biasing of this junction. For a transistor operating in the hysteresis mode, we show that the potential barrier height for electron injection across the source-channel junction increases for increasing negative gate voltages during retrace. This results in a gate controlled turn-off of the drain current for SOI and vertical n-MOSFETs operating in the regenerative mode.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectHysteresisen_US
dc.subjectMOSFET circuitsen_US
dc.subjectElectronsen_US
dc.subjectPlasma temperatureen_US
dc.subjectImpact ionizationen_US
dc.subjectVoltage controlen_US
dc.titleHysteresis behavior in 85-nm channel length vertical n-MOSFETs grown by MBEen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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