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Title: | Device-circuit co-design for high performance level shifter by limiting quasi-saturation effects in advanced DeMOS transistors |
Authors: | Rao, V. Ramgopal |
Keywords: | EEE Performance evaluation Doping Delays Transistors Optimization |
Issue Date: | 2016 |
Publisher: | IEEE |
Abstract: | This paper presents a device-circuit co-design methodology for a DeMOS 5V GHz-speed high voltage level shifter. The limiting quasi-saturation effect is addressed by a codesign methodology. The co-design methodology is applied to the STI-DeMOS in a calibrated setup using experimental data. As a result, a 15% improvement in the speed is achieved for a high-performance level shifter circuit. |
URI: | https://ieeexplore.ieee.org/document/7589264 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12794 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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