Device-circuit co-design for high performance level shifter by limiting quasi-saturation effects in advanced DeMOS transistors

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DC Field	Value	Language
dc.contributor.author	Rao, V. Ramgopal	-
dc.date.accessioned	2023-11-01T10:48:35Z	-
dc.date.available	2023-11-01T10:48:35Z	-
dc.date.issued	2016	-
dc.identifier.uri	https://ieeexplore.ieee.org/document/7589264	-
dc.identifier.uri	http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12794	-
dc.description.abstract	This paper presents a device-circuit co-design methodology for a DeMOS 5V GHz-speed high voltage level shifter. The limiting quasi-saturation effect is addressed by a codesign methodology. The co-design methodology is applied to the STI-DeMOS in a calibrated setup using experimental data. As a result, a 15% improvement in the speed is achieved for a high-performance level shifter circuit.	en_US
dc.language.iso	en	en_US
dc.publisher	IEEE	en_US
dc.subject	EEE	en_US
dc.subject	Performance evaluation	en_US
dc.subject	Doping	en_US
dc.subject	Delays	en_US
dc.subject	Transistors	en_US
dc.subject	Optimization	en_US
dc.title	Device-circuit co-design for high performance level shifter by limiting quasi-saturation effects in advanced DeMOS transistors	en_US
dc.type	Article	en_US
Appears in Collections:	Department of Electrical and Electronics Engineering

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