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dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-11-02T07:18:59Z-
dc.date.available2023-11-02T07:18:59Z-
dc.date.issued2015-06-
dc.identifier.urihttps://ieeexplore.ieee.org/document/7285240-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12805-
dc.description.abstractIn this work, two drain extended NMOS (DeNMOS) devices, one with only planar gate and another with both planar gate and gate in a trench under the gate-drain overlap region (called trench-gate DeNMOS) are investigated. The latter device shows improved ON-state performance due to greater spacecharge control with addition of trench gate. The OFF-state breakdown physics is also compared with conventional DeNMOS device. Due to greater field spreading in the trench-gate device under OFF-state conditions, a distinct base-push effect is not observed, unlike conventional device. The oxide reliability in trench-gate device improves with an additional offset in the drift region. Therefore, the trench-gate DeNMOS can be used as an alternative to improve input/output (I/O) device performance and reliability in advanced system-on-chip (SoC) applications.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectLogic gatesen_US
dc.subjectElectric breakdownen_US
dc.subjectSemiconductor process modelingen_US
dc.subjectImpact ionizationen_US
dc.titleOn the breakdown physics of trench-gate drain extended NMOSen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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