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http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12809| Title: | Drain extended MOS device design for integrated RF PA in 28nm CMOS with optimized FoM and ESD robustness |
| Authors: | Rao, V. Ramgopal |
| Keywords: | EEE Radio frequency Logic gates Electric fields CMOS integrated circuits Electrostatic discharges Robustness |
| Issue Date: | Feb-2015 |
| Publisher: | IEEE |
| Abstract: | This paper explores drain extended MOS (DeMOS) device design guidelines for an area scaled, ESD robust integrated radio frequency power amplifier (RF PA) for advanced system-on-chip applications in 28nm node CMOS. Simultaneous improvement of device-circuit performance and ESD robustness is discussed for the first time. By device design optimization a 45% increase in gain and 25% in power-added efficiency of RF PA at 1GHz, and 5× improvements in ESD robustness are reported experimentally. |
| URI: | https://ieeexplore.ieee.org/document/7046974/authors#authors http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12809 |
| Appears in Collections: | Department of Electrical and Electronics Engineering |
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